In a synchronous digital system, a clock signal is used to define a time reference for the movement of data within that system. A clock distribution network (often referred to as a clock distribution tree) distributes the clock signal(s) from a common point to the various synchronous elements within that clock domain. FIG. 1 illustrates a simplified example of a clock distribution network 100. Clock distribution networks typically comprise the greatest fan-out of all signals within a synchronous digital system, and typically operate at the highest speeds of any signals, either control or data, within the synchronous system. Since the transmission of data signals relies on a temporal reference provided by clock signals, the waveforms of those clock signals must be particularly clean and sharp. Furthermore, because long interconnect lines become significantly more resistive as line dimensions are decreased, clock signals are particularly affected by technology scaling.
Synchronous digital systems typically comprise cascaded banks of sequential registers with combinational logic between each set of registers. The functional requirements of the digital system are satisfied by the various logic stages, with timing requirements between the logic stages being controlled through appropriate clock signals provided to the respective registers. The proper design of the clock distribution network ensures that these critical timing requirements are satisfied. Thus, the reliability and accuracy of the clock signals has a significant impact on the maximum performance of the entire synchronous system.
Furthermore, the clock distribution network is often responsible for a significant proportion of the overall power consumption of an integrated circuit device therefor. One power saving technique often implemented within synchronous digital systems is dynamic frequency scaling (DFS), wherein the frequency of the clock signal(s) may be dynamically controlled to either reduce power consumption by reducing the frequency of the clock signal(s) or to increase performance by increasing the frequency of the clock signal(s). Such dynamic frequency scaling is often implemented with dynamic voltage scaling (DVS), whereby the supply voltage to elements within the synchronous digital system may be increased or decreased depending on the system requirements; the combined implementation of DFS and DVS typically referred to as dynamic voltage and frequency scaling (DVFS). For example, when low power consumption is a priority, the voltage supply may be reduced along with the clock frequency. Conversely, when high performance is a priority, the voltage supply may be increased along with the clock frequency, to enable fast switching of signals.
A mesh clock tree configuration is a known clock distribution network configuration comprising shorting between clock tree layers with the same propagation delay. This results in a multi-driven mode in which meshed clock nodes are driven by multiple clock tree registers. In this manner, skew between different clock tree branches may be reduced. Ideally, a mesh clock tree configuration should be implemented over an H-tree clock tree design, where all branches are totally symmetrical. FIG. 2 illustrates a simplified example of such an H-tree design 200. Within an ideal H-tree design, on chip variation is the only cause for skew, which can be reduced by shortening the length of branches. Thus, in an ideal H-tree clock tree design, branches will have skew, and so current through shorting lines will be limited.
In practice, H-tree implementation has many constraints due to the impact that it can have on functional components within the synchronous digital system. For example, memory elements typically have constraints for their placement, often resulting in an asymmetrical, non-rectangular layout. Furthermore, imposing fixed pre-placement of clock buffers and pre-routing of clock distribution nets with shielding can impact critical paths of the functional design for a synchronous digital system. Additionally, H-tree clock tree power consumption in low activity applications is higher than a normal clock tree configuration. Normal clock tree configurations are typically balanced for typical PVT (process, voltage, temperature) conditions, but suffer from elevated skew over PVT (process, voltage temperature) variations due to the non-symmetrical nature of branches within the network. Such elevated skew can be problematic for both setup and hold timing closure. The skew within a normal clock distribution network configuration may be reduced by applying connections between clock layers with the same propagation delay to create shorts there between. FIG. 3 illustrates a simplified example of the clock distribution network 100 of FIG. 1, comprising a normal clock tree configuration and with shorting connections applied between clock layers with the same propagation delay, as illustrated by the broken lines at 300. In this manner, a crude mesh clock tree may be achieved from a normal clock tree configuration, simplifying the practical implementation of such a mesh clock tree. However, the non-symmetrical nature of the branches within such a crude mesh clock tree design typically result in a high current through shorting lines, thereby increasing the power consumption of the clock distribution network.
Thus, a mesh clock tree implementation enables low skew to be achieved throughout the digital synchronous system, which enables good setup and hold timing closure, and thus enables high speed applications to be achieved. However, ideal mesh (H-Tree) clock tree implementations are difficult to implement in practice, and more crude mesh clock tree implementations suffer from high power consumption which is undesirable for low power applications. Conversely, a normal clock tree implementation has a lower power consumption than a mesh clock tree implementation at lower speeds, but suffers from high skew (especially over process/voltage/temperature ranges), which is problematic for high speed applications due to setup and hold timing issues. Accordingly, neither a mesh clock tree implementation nor a normal clock tree implementation provides an ideal solution across both high speed and low power configurations, for example such as may be desired within a digital synchronous system in which DVFS is implemented.